From Intelligent Recognition to Chip Architecture: Yuan Ze University Won Outstanding Paper Awards at TANET 2025

The Department of Computer Science and Engineering, Yuan Ze University, demonstrated strong research capability at the 2025 Taiwan Internet Conference (TANET 2025), receiving recognition across three major areas: artificial intelligence, human-factor detection, and system-on-chip architecture.

Two research teams supervised by Professor Ming-Yi Lin each won an Outstanding Paper Award, making Yuan Ze University one of the highlights of the conference.

Among the award-winning studies, Tzu-Yang Liu received the Outstanding Paper Award in the “Intelligent Recognition” category for his research titled “A Multimodal Fusion Method Combining rPPG and Visual Features for Driver Fatigue Detection.” The study integrated remote photoplethysmography (rPPG) with visual recognition techniques, incorporating 24 features, including facial landmarks, heart rate estimation, eye and mouth parameters, gaze direction, and head pose. Both early-fusion and late-fusion strategies were evaluated. Results showed that, on the RLDD dataset, early fusion combined with Gradient Boosting and feature selection achieved an accuracy of 78.73%, significantly outperforming single-modality and late-fusion approaches. The integration of rPPG and visual signals also improved model robustness. The study further verified the low-error performance of the CHROM algorithm for heart rate estimation, highlighting the feasibility and application potential of multimodal fatigue detection technologies.

Another paper, titled “A Self-Repairing BISR Memory Architecture Design Integrating BIST and OTP,” was jointly completed by Yi-Hsiang Wang, Chun-Hsien Shen, Che-Chi Li, Yu-Chieh Huang, and Wei-Kuan Chiang, and received the Outstanding Paper Award in the “System-on-Chip and Computer Architecture” category. The research proposed a memory error-repair architecture that integrated Built-In Self-Test (BIST) with One-Time Programmable (OTP) memory, enabling automatic fault detection and immutable recording of failure information. The OTP programming process was controlled by a finite state machine (FSM), with multiple verification tests ensuring the accuracy of recorded fault data. The overall architecture was implemented in Verilog HDL and synthesized using Synopsys Design Compiler. Experimental results demonstrated high fault coverage and reliable repair capability, making the design suitable for high-stability system-on-chip (SoC) applications.

Professor Ming-Yi Lin noted that, whether in AI-based driver fatigue detection or in memory reliability and self-repair architecture design, the students demonstrated a high level of commitment, innovation, and problem-solving ability. He emphasized that “the value of research lies not only in technological breakthroughs, but also in responding to real-world needs.” The dual awards once again confirmed the Department of Computer Science and Engineering at Yuan Ze University as a leader in the fields of artificial intelligence, human-centered technology, and system-on-chip design.